Signal Integrity for High-Speed Memory and Processor I/O

Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course teaches you about high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using CAD packages. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules and practical hands-on labs.

Level

Intermediate

Training Duration

2 days

Who Should Attend?

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users, of Xilinx products, who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Prerequisites

Xilinx FPGA design experience preferred (equivalent to the Fundamentals of FPGA Design course)

Software Tools

• Mentor Graphics HyperLynx
• Cadence SPECCTRAQuest

Skills Gained

After completing this training, you will be able to:

• Identify when signal integrity is important and relevant
• Interpret an IBIS model and correct common errors
• Apply appropriate transmission line termination
• Understand the effect loading has on signal propagation
• Mitigate the impact of jitter
• Manage a memory data bus
• Understand the impact of selecting a PCB stackup
• Differentiate between on-chip termination and discrete termination

Course Outline

Day 1

• Introduction
• Transmission Lines
• Lab 1: Mentor or Cadence
• IBIS Models
• Lab 2: Mentor or Cadence
• Lab 3: Mentor or Cadence
• High-Speed Clock Design
• Lab 4: Mentor or Cadence
• SRAM Requirements
• Lab 5: Mentor or Cadence

Day 2

• Physical PCB Structure
• On-Chip Termination
• SDRAM Design
• Lab 6: Mentor
• Managing an Entire Design

Lab Descriptions

Note: Labs feature the Mentor Graphics or Cadence flow. For private training, please specify your desired flow to your registrar or sales contact. For public classes, flow will be determined by the instructor, based upon class feedback.

Mentor Labs

• Lab 1: Opening the appropriate Mentor simulator
• Lab 2: Hands-on signal integrity observation of reflection and propagation effects
• Lab 3: Using an IBIS simulator to study basic transmission line effects
• Lab 4: Using saved simulation information to perform power calculation. Also, additional clock simulations
• Lab 5: Observing the effects of coupling on transmission lines
• Lab 6: Demonstrating how an SDRAM module can be handled with an EBD model

Cadence Labs

• Lab 1: Opening the appropriate Cadence simulator
• Lab 2: Analysis of a simple clock net
• Lab 3: Signal integrity effects caused by multidrop clock networks
• Lab 4: Crosstalk analysis
• Lab 5: Address and data analysis