Comprehensive SystemVerilog

SystemVerilog is a significant new language based on the widely used and industry-standard Verilog® hardware description language. The SystemVerilog extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture. SystemVerilog is expected to become IEEE standard 1800 in 2005.

Comprehensive SystemVerilog is the first public course to offer a one-stop solution for evaluators and new users, covering both design and verification. Presented from a vendor independent perspective, approximately 50% of class time is dedicated to carefully designed workshops using the delegate's choice of leading EDA tools (including Mentor Graphics QuestaTMSim, Synopsys VCS® and Design Compiler®).

Comprehensive SystemVerilog comprises 3 modules, which focus on the following key areas:

• SystemVerilog as a 'better Verilog', emphasising synthesis and bus modeling
• SystemVerilog assertions for design and verification
• Testbench automation techniques to increase verification productivity
• Verification of Verilog or VHDL designs using SystemVerilog

Comprehensive SystemVerilog comprises

• Fundamentals of SystemVerilog: (days 1-2) provide hands-on training for existing users of Verilog or VHDL. The module trains engineers in the practical use of SystemVerilog as a design language and includes RTL synthesis. The module focuses on the features of SystemVerilog that are currently supported by the tools, and provides tuition in the new methodologies that both the language and the tools enable.
• SystemVerilog Assertions: (day 3) provides in-depth tuition in the use of SystemVerilog Assertions (SVA) in the context of an assertion-based verification methodology for digital electronic design.
• SystemVerilog Testbench Automation: (day 4-5) describes how to use SystemVerilog's testbench automation capabilities with a constrained Random Verification Methodology. This includes: structuring testbenches, using cycle-based timing, object-oriented modelling using classes, and functional coverage. These features enable you to write testbenches at higher levels of abstraction and be more productive than is possible with standard hardware description languages.

Who should attend?

• Hardware design engineers who wish to become skilled in the practical use of SystemVerilog for digital hardware design and verification
• Verification engineers who wish to become skilled in the practical use of SystemVerilog for creating testbenches

What will you learn?

• The SystemVerilog core language, data types and interfaces
• How to synthesize hardware from a SystemVerilog description
• How to call functions written in C from SystemVerilog models and vice versa
• How to write and apply assertions and use an assertion-based verification methodology
• How to model busses, and apply efficient synthesis and verification techniques
• How to create structured testbenches and use cycle-based timing
• How to use object-oriented programming as implemented by SystemVerilog classes and how to apply this to constrained-random test stimulus generation
• How to create and use functional coverage information

Prerequisites

A good working knowledge of Verilog or VHDL is essential. This is not suitable as a first course in a hardware description language. Engineers who have not used either VHDL or Verilog, should attend the Doulos Comprehensive Verilog course before taking SystemVerilog training.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The course set components include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips