Serial RapidIO Controller Core

Index

General Description
Features
Applications
Deliverables
Licensing
Datasheet
Reference Design
Pricing and Additional Information

General Description

The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.

So_ip_srio_ctrl soft core is fully compliant with the RapidIO 2.2 specification, and supports 1.25, 2.5, 3.125, and 5.0 Gbit/s data transfer rates.

So_ip_srio_ctrl core implements physical, transport and link layers, as defined in the RapidIO specification. It uses Xilinx's MGT transceivers to implement physical signaling required by the RapidIO specification. For the interface with the host processor IP core uses a highly configurable user interface.

So_ip_srio_ctrl core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.

The so_ip_srio_ctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. The so_ip_srio_ctrl core can be evaluated using Xilinx Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for the selected Xilinx evaluation platform that allows the user to connect it’s Serial RapidIO enabled device to the So-Logic's so_ip_srio_ctrl core and evaluate system performance under different transfer scenarios.

For more information about the Serial RapidIO controller core please consult the corresponding datasheet.

Features

• Fully compliant with the RapidIO specification revision 2.2,
• Simple transaction interface with Host processor and DMA Engine,
• Configurable FIFOs implemented by BlockRAM in both transmit and receive paths,
• Register file containing all necessary architectural registers providing total software control of IP core,
• Low frequency operation,
• Supports 1.25, 2.5, 3.125 and 5.0 Gbit/s data transfer rates,
• Supports all commands defined in the I/O Logical specification,
• Supports Doorbell and Data message operations defined in the Message Passing Logical specification,
• Hardware support for:
  • Clock and Data Recovery,
  • Lane Synchronization,
  • 8b/10b coding and decoding,
  • CRC generation and checking,
  • Scrambler/Descrambler,
  • Packet/Control Symbol Assembly and Deassembly.
• Support for various Xilinx's MGT transceivers,
• Reference design available for various Xilinx Evaluation Platfoms.

Applications

• Wireless: Baseband cards and backplanes in LTE/WiMAX/WCDMA/TD-SCDMA;
• Defense & Aerospace: radar, sonar nav systems;
• Video and imaging;
• Industrial control systems;
• Storage: low latency, and high bandwidth memory interface.

Deliverables

Source code (source code license only)

• VHDL Source Code

VHDL verification environment

• Tests with reference responses

Technical documentation

• Installation notes
• HDL core specification
• Datasheet

Instantiation templates

Reference design

Technical support

• IP Core implementation support
• Variable length maintenance
• Delivery of IP Core updates, minor and major changes
• Delivery of documentation updates
• Telephone & email support

Licensing

Netlist License

• Post-synthesis netlist
• Self checking testbench
• Test vectors for testing the core
• Place&Route scripts
• Constraints
• Instantiation templates
• Documentation

VHDL Source License

• VHDL RTL source code
• Complete verification plan together with testbenches needed to verify correct operation of the core
• Self checking testbench
• Vectors for testing the functionality of the core
• Simulation & synthesis scripts
• Documentation

Datasheet

For more information about the So-Logic's Serial RapidIO Controller core, please see the following datasheet:

• so_ip_srio_ctrl Datasheet

Reference Design

Reference design for the Serial RapidIO Controller core is avaiable upon the request. Reference design comes in a form of bit file for selected Xilinx Evaluation Platforms. Using this reference design, customer can connect it's Serial RapidIO enabled device to the So-Logic's Serial RapidIO Controller core and evaluate the functionality and performance of the core. For more information about the reference design, please contact So-Logic at ip_srio_ctrl@so-logic.net.

Pricing and Additional Information

Pricing of the Serial RapidIO Controller core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the Serial RapidIO Controller core, please contact So-Logic at:

Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44
email: ip_srio_ctrl@so-logic.net